A New Kind Of Chip For Quantum Technology

Today, we are living in the midst of a race to develop a Quantum computer, one that could be used for practical applications. This device, built on the principles of quantum mechanics, holds the potential to perform computing tasks far beyond the capabilities of today's fastest supercomputers. Quantum computers and other quantum-enabled technologies could foster significant advances in areas such as cybersecurity and molecular simulation, impacting and even revolutionizing fields such as online security, drug discovery and material fabrication.

An offshoot of this technological race is building what is known in scientific and engineering circles as a "quantum simulator"—a special type of quantum computer, constructed to solve one equation model for a specific purpose beyond the computing power of a standard computer. For example, in medical research, a quantum simulator could theoretically be built to help scientists simulate a specific, complex molecular interaction for closer study, deepening scientific understanding and speeding up drug development.

But just like building a practical, usable quantum computer, constructing a useful quantum simulator has proven to be a daunting challenge. The idea was first proposed by mathematician Yuri Manin in 1980. Since then, researchers have attempted to employ trapped ions, cold atoms and superconducting qubits to build a quantum simulator capable of real-world applications, but to date, these methods are all still a work in progress.

Recent advances in superconducting system design and fabrication have led to several successful implementations of prototypical quantum simulators that demonstrate small-scale quantum systems. However, there have been challenges in enlarging these systems to a usable size, as well as operating difficulties when attempting to use superconducting systems to simulate actual quantum materials.

Now, a University of Washington research team led by Arka Majumdar, UW associate professor of both physics and electrical and computer engineering, has moved this effort a significant step ahead. The team demonstrated in Nature Communications that a new kind of silicon photonic chip could work as a solid foundation for building a quantum simulator, one with useful applications in the real world.

Majumdar is an expert in optics, photonics, and the development of quantum technologies. At the UW, in addition to his teaching and research responsibilities, he is a co-chair of QuantumX and a member of the Institute for Nano-Engineered Systems.

"We've shown that photonics is a leading contender for quantum simulation, and photonic chips are a reality," Majumdar said. "We believe that these chips can play a very important role in building a quantum simulator."

"This is a very good platform for realizing a useful quantum simulator that could be scaled to large sizes," added Abhi Saxena, lead author of the paper and recent UW ECE alumnus. Saxena graduated in 2023 with his doctoral degree and now works for the National Institute of Standards and Technology (NIST) in Boulder, Colorado.

Other members of the research team include Arnab Manna, a doctoral student in the physics department and UW ECE Assistant Professor Rahul Trivedi, a quantum systems expert who assisted the group with theoretical aspects of their research.

The advantages of a silicon photonic chip—scalable, measurable, programmable

Photonics is a branch of optics (the study of behavior and properties of light) that applies generation, detection, and manipulation of light to enable a wide range of technologies, such as lasers, fiber optics, and light-emitting diodes (LEDs). A key advantage photonics has over other methods of building a quantum simulator platform is that photonic devices can be fabricated in CMOS foundries, which have been used for decades to produce semiconductor chips.

"The fabrication process that we have for this chip can directly latch onto the already well-matured silicon fabrication that we do for transistors and other computer chips," Saxena said. "Whereas for other quantum simulator platforms that's not feasible, even though many of them have already demonstrated prototypical devices."

As a case in point, the research team created their silicon photonic chip at the Washington Nanofabrication Facility on the UW campus. Their fabrication method will help lower production costs for building a quantum simulator, and perhaps more importantly, make it possible to scale the chip up enough for it to be usable in a wide range of quantum simulation devices.

At the heart of the chip the team designed is a "photonic coupled cavity array." This array is a pseudo-atomic lattice made up of eight photonic resonators. It is a place where photons can be confined, raised and lowered in energy, and moved around in a controlled manner, essentially forming circuits.

Important technical innovations by the team related to the array include creating a mathematical algorithm that allowed them to map, or characterize the chip in detail, using only information available on the boundaries of the chip, and designing a new kind of architecture for heating and independently controlling each cavity in the array, which let the team program the device. According to Majumdar and Saxena, these two innovations on a silicon photonic chip have never been accomplished before.

"We are demonstrating everything on a chip, and we have shown scalability, measurability and programmability—solving three of the four major obstacles to using a silicon photonic chip as a platform for a quantum simulator," Majumdar said. "Our solution is a small size, it is not misalignment-prone, and we can program it."

What the future holds

Moving forward, the research team seeks to solve what they see as the fourth, and final, major obstacle to building a fully realized quantum simulator, creating a condition called "nonlinearity." Unlike the electrons commonly found in electronic circuits, which repel each other because of their negative electrical charge, photons, by their nature, do not interact with each other. An equivalent interaction is needed in a quantum simulator to create nonlinearity and complete the circuitry. The team is currently exploring several different approaches to address this issue.

Also on the research team's agenda is to fine-tune their silicon photonic chip, optimizing it for standard chip foundries, so the chip can be manufactured at semiconductor fabrication plants around the world. Majumdar and Saxena both said that this aspect of development would be, relatively speaking, an easier hurdle, and they expressed optimism about the impact their chip will have.

"Through this work, we presented a solid foundation for a platform that demonstrates photonics and the semiconductor-based technology we are using as viable alternatives to create quantum simulators," Saxena said. "I think that up until now, many in the scientific and engineering communities have generally avoided considering photonics for this purpose. But our work shows that it is realistically possible, so it is a very good incentive for more people to begin moving in this direction."

More information: Abhi Saxena et al, Realizing tight-binding Hamiltonians using site-controlled coupled cavity arrays, Nature Communications (2023). DOI: 10.1038/s41467-023-41034-x

Citation: A new kind of chip for quantum technology (2023, September 27) retrieved 8 October 2023 from https://phys.Org/news/2023-09-kind-chip-quantum-technology.Html

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Inside Intel's Chip Factory, I Saw The Future. It's Plain Old Glass

Computer processors are some of the most complicated devices humans ever created. Engineers pluck just the right combinations of atoms out of the periodic table to make materials that can steer cascades of electrons through billions of finely etched circuits at ultrahigh speeds.

But the next breakthrough to make our laptops more efficient and AI more powerful could come from plain old glass. I've just seen firsthand how it works.

Intel will detail the glass technology at its Innovation event Tuesday in San Jose, California. I was one of just two journalists who got the first look at how this technology works, donning a stuffy head-to-toe "bunny suit" to enter Intel's ultraclean CH8 factory in Chandler, Arizona. There, in a hulking white high-tech building in the Phoenix area's scorching desert landscape, Intel transforms sheets of glass the size of a small tabletop into paperclip-sized rectangular sandwiches of circuitry built with some of the same techniques as the processor itself.

Intel has begun a years-long transition to new technology that rests processors on a bed of glass instead of today's epoxy-like organic resin. The new glass foundation, called a substrate, offers the speed, power and real estate necessary for the chip industry's shift to new technology packaging multiple "chiplets" into a single larger processor.

In short, that means a new way to sustain Moore's Law, which charts progress in cramming more circuitry elements called transistors into a processor. The A17 Pro processor in Apple's new iPhone 15 Pro has 19 billion transistors. Intel's Ponte Vecchio supercomputing processor has more than 100 billion. By the end of the decade, Intel expects processors with -- if you can imagine it -- a trillion transistors.

Intel relied on this chiplet approach to catch up to competitors with superior processor manufacturing abilities. But now Intel can use it to outpace rivals in an era when exploding demand for new processing power has surpassed the industry's ability to deliver it, said Creative Strategies analyst Ben Bajarin. And Intel's glass substrate technology demonstrates Intel's packaging prowess.

"One hundred percent, this is going to end up leading to a competitive advantage," Bajarin said.

What it means for you, a few years down the line, is supercharged laptops and AI tools that are even more stunningly smart than what you're seeing today. 

Why the chip industry will shift to glass substrates

The whole chip industry will make the glass transition at least for high-end processors to cope with chipmaking challenges, and Intel has the lead, said FeibusTech analyst Mike Feibus.

With more than a decade's work collaborating with academics and testing new methods, a staff of 600 headquartered at Chandler has turned research and development into a functioning manufacturing line.

"Basically, the innovation is done," said Ann Kelleher, the executive vice president leading technology development at Intel. The glass substrate technology "gives us an ability to ultimately get higher performance for our products."

I Got an Early Look at Intel's Glass Packaging Tech for Faster Chips See all photos

Those are bold words from a company that's halfway through a four-year effort to recover the prowess it lost to Taiwan Semiconductor Manufacturing Co. and Samsung, chip "foundries" that build processors for hundreds of electronics companies. When Intel manufacturing progress stalled for several years starting nearly a decade ago, it lost its once formidable lead to the two Asian chipmakers.

The glass technology underneath a processor won't arrive until the second half of the decade, and when it does, it'll appear first underneath the biggest, most power-hungry chips, the ones that perch in thousands of servers stacked up in data centers operated by huge "hyperscalers" like Google, Amazon, Microsoft and Meta.

That's because glass brings several advantages to these hot and huge chips, said Rahul Manepalli, an Intel fellow who leads Intel's module engineering work.

It can accommodate 10 times the power and data connections as today's organic substrates so more data can be pumped in and out of a chip. It doesn't warp as much, critical to ensuring processors lie flat and connect properly to the outside world and thus enabling 50% larger chip packages. It transmits power with less waste, meaning chips can run either faster or more efficiently. And it can run at a higher temperature, and when it heats up, it expands at the same rate as silicon to avoid mechanical failures.

Glass will enable a new generation of server and data center processors, successors to mammoth beasts like the Intel Xeons that can run cloud computing services like email and online banking and Nvidia's artificial intelligence processors that have exploded in popularity as the world embraces generative AI.

But as glass substrates mature and costs come down, it'll spread beyond data centers to the computer sitting on your lap.

The inside of CH8, an Intel facility in the Phoenix suburb of Chandler, Arizona, is packed with equipment for manufacturing the substrates that lie beneath processors and other packaging technology. It's where Intel developed its EMIB technology in past years and is working on glass substrates today. Stephen Shankland/CNET

"Clearly we see this going into client applications," Manepalli said, using Intel's term for personal computers.

Chipmaking recovery: Five nodes in four years

Under the leadership of Chief Executive Pat Gelsinger, who rejoined Intel in 2021, Intel is trying to claw its way back to the leading edge. At every press conference and quarterly earnings call, Intel executives intone the mantra "five nodes in four years," referring to the effort to advance through five big new chip manufacturing steps at a torrid pace to catch up to TSMC and Samsung and then surpass them by 2025.

Kelleher, in charge of the effort, declares two of the steps complete so far and the rest proceeding on schedule. In a briefing I attended at Intel's Chandler facilities, with many of her top executives gathered around a conference table, the no-nonsense Irish electrical engineer makes it clear you don't want to be the person to disappoint her.

"For those who know me well, and this team may chuckle, I don't like missing a milestone," she said. The executives do indeed chuckle, but their slightly nervous tone makes it clear it's far from a joking matter.

"5N4Y," as the recovery effort is called, is a difficult, expensive and ambitious recovery plan for a company that fell so far behind. So far, Gelsinger, Kelleher and thousands of engineers are delivering the goods.

"With every passing year, I have a higher degree of confidence that they will hit those milestones," Bajarin said.

A package deal

But even if Intel recovers its lead in the manufacturing process called lithography that etches transistors onto a silicon surface, the company and its rivals all face a serious problem: building the housing that attaches those chips to a circuit board. That's where packaging and glass substrates come into the picture.

Intel's 8086 chip, the 1978 precursor to every PC and server processor that Intel has made since, was a flat square of silicon with 29,000 transistors. To protect it and plug it into a circuit board, it was housed in a package that looked like a flat caterpillar. Forty metal legs carried power and data to the chip.

The Intel 8086 processor package had 40 electrical connections for power and data that gave the chip a caterpillar look. Modern chips have thousands of connections, now just small metal patches on the underside of the package. Intel

Since then, processor packaging has advanced dramatically. It once was relatively crude, but now the boundary between chipmaking and packaging are blurring, Kelleher said. Packaging processes now use lithography machines to etch their own circuitry, although not nearly as finely as on processors. 

Over the decades, processors moved from caterpillar legs to hundreds of pins that looked like a tiny bed of nails covering the bottom of a processor. (If you ever built a PC back in the day, slotting a processor into its socket, you'll know what I'm talking about.) But eventually that approach didn't offer enough electrical contacts to the circuit board, either.

So today's packages have flat metal contact patches on the bottom of the package. The chip is installed when hundreds of pounds of force mash it onto a circuit board.

A metal cap atop a processor draws away waste heat that otherwise would crash a computer. And beneath the processor is a substrate with an increasingly complex, three-dimensional network of power and data connections to link the chip to the outside world.

What lies beneath

There are challenges moving from today's organic substrates to glass. Glass is brittle, so it must be handled carefully, for example.

To ease the transition, Intel is adapting glass-handling equipment from experts who already know how to handle it without breaking: the display industry, which makes everything from tiny smartwatch screens to enormous flat-panel TVs. They also have to etch circuitry onto glass and have developed many of the needed ultrapure materials and careful handling processes.

But there are differences. Flat-panel displays have sensitive electronic elements only on one side, so glass can glide through factories on rollers. Intel builds a sandwich of materials and circuitry called redistribution layers onto both sides of the glass, so its machines must in effect hold the glass only by the edges.

In one step of the process I saw in Intel's CH8 facility, a sealed container with a stack of nearly square glass substrates plugs into the front of a bright white machine about the size of a double-decker bus. Each panel is carefully withdrawn from the container, pulled into the machine, pivoted into a vertical orientation and slurped deeper inside for new layers to be added to the sandwich.

As with everything in Intel, it's designed for high-volume manufacturing, not low-scale R&D projects.

"I walked away with a greater appreciation of not just the technology but also Intel's capabilities to do advanced packaging," said Bajarin, one of the two journalists and three analysts who toured CH8. "It made me a lot more optimistic about their prospects."

Packaging boosts Intel Foundry Services

Intel packaging technology should be useful for its own data center processors. It also is important for Intel's ambitious business overhaul to become a chip foundry like TSMC and Samsung, building processors for other companies through its Intel Foundry Services division.

Packaging is a service Intel can provide even if it makes none of the chips and chiplets that go into a package. But then it can lead to a deeper customer deal in which intel fabrication facilities, or "fabs," build the silicon processor chips and chiplets, too.

"We have both competitiveness and capacity," said Mark Gardner, the senior director who leads the Foundry Advanced Packaging group at IFS. Signing on a packaging customer is a bit easier than signing on a chipmaking customer, with fewer technology complications and shorter lead times, he said.

A real-world example of Intel's packaging technology is Intel's Sapphire Rapids, a large Xeon processor for data centers. Intel combines four CPU tiles, each also called a die or chiplet, into one larger processor. Intel's EMIB (embedded multidie interconnect bridge), a thin sliver of silicon underneath the edges where the tiles abut, supply data links across the processor so it behaves like one larger unit. Stephen Shankland/CNET

But in customer deals for packaging can lead to the deeper relationship that extends into chipmaking, in particular with the Intel 18A chipmaking process the company expects will surpass TSMC and Samsung in 2024.

"It's a foot in the door," Gardner said. "There's one customer in particular [for which] that trajectory of packaging first and advanced packaging then 18A is working well."

The power of packaging

Packaging is central to the Intel of today. Its newest Sapphire Rapids member of the Xeon server processor line uses a technology called an embedded multidie interconnect bridge, or EMIB, to link four chiplets into one large processor. A smaller chiplet (each also called a die) is less likely than a large one to be spoiled by a manufacturing defect, so manufacturing yields improve.

At Tuesday's Innovation event, Intel will shine a spotlight on Meteor Lake, its next-generation Core processor for PCs. It employs a different processor packaging technique called Foveros that stacks chiplets in three dimensions like pancakes -- and in Meteor Lake's case, most of the chiplets are Intel designs actually manufactured by its top rival, TSMC. Meteor Lake is expected to arrive in PCs later this year.

With those two products, along with more exotic processors like Ponte Vecchio, Intel has moved the bulk of its processor products to chiplet designs. In 2024, Intel plans to deliver more chiplet-based designs, including the big Granite Rapids and bigger Sierra Forest Xeon chips and the Arrow Lake PC chips expected in 2024.

Intel is the biggest fan of assembling "disaggregated" slices of silicon into bigger processors, but others have embraced it, too.

The M2 Ultra, the top-end Mac processor that completed Apple's two-year transition away from Intel chips, joins two M2 Max chips with a high-speed connection. And AMD, which relies on TSMC and Samsung to build its designs, has gained market share at Intel's expense with server chips that employ multiple chiplets.

It's unclear how much of the processor business will move from "monolithic," single-die designs to chiplet designs. There are still cost and simplicity advantages to avoiding advanced packaging. But it's clear the biggest processors -- the server and AI brains in data centers -- will become sprawling complexes of interlinked chiplets.

And that's where glass substrates should come in handy, with enough area, communication links and power delivery abilities to give chip designers room for growth.

"You start to hit your head on a technology," Feibus said, "and it's time to find a new way to do things." 

IPhone 15 Pro's A17 Chip Said To Feature 6 GPU Cores, Support For … – MacRumors

Apple's upcoming A17 chip that is set to be used in the iPhone 15 Pro and ‌iPhone 15 Pro‌ Max models includes a 6-core CPU and a 6-core GPU, according to leaker Unknownz21. The current A16 chip has a 6-core CPU and a 5-core GPU, so the A17 will bring notable GPU improvements to the new higher-end iPhone models.The A17 chip will feature a 3.70GHz maximum clock rate, up from 3.46GHz in the A16 chip. Notably, the information shared by Unknownz21 suggests that the ‌iPhone 15 Pro‌ models will feature the same 6GB RAM that's available in the iPhone 14 Pro models. Prior rumors have said the ‌iPhone 15 Pro‌ and Pro Max would have 8GB RAM, which the leaker says is "unlikely," but not impossible.

Built on a new 3-nanometer process, the A17 chip will bring speed and efficiency improvements to the ‌iPhone 15 Pro‌ and Pro Max. We should see a decent increase in GPU performance along with faster CPU speeds and perhaps better battery life compared to the A16, which is built on a 4-nanometer process. Performance could increase by 10 to 15 percent, while power consumption could be down by up to 30 percent.Apple A17 – t8130 – Coll 6 CPU Cores + 6 GPU Cores3.70 GHz6GB LPDDR5 DRAM – Micron/SamsungTSMC 3nm Process LPDDR = Low Power Double Data Rate SDRAM The A17 is used by both the D83 and D84, also likely planned for D47 and D48 (16 series), as the D9x will use t8140 (A18). — Unknownz21 🌈 (@URedditor) August 9, 2023Because 3nm technology is new, the A17 chip is expensive to manufacture, which means it will only be available in the ‌iPhone 15 Pro‌ and ‌iPhone 15 Pro‌ Max. The standard iPhone 15 models will adopt the A16 chip, which is currently limited to the ‌iPhone 14‌ Pro and ‌iPhone 14‌ Pro Max.Apple is expected to unveil the new iPhones in September, and current signs suggest the ‌iPhone‌ event will be held on Tuesday, September 12. For more on what's coming, we have dedicated iPhone 15 and iPhone 15 Pro roundups that aggregate all of the rumors we've heard to date.Get weekly top MacRumors stories in your inbox.Our comprehensive guide highlighting every major new addition in iOS 17, plus how-tos that walk you through using the new features.Get the most out your iPhone 15 with our complete guide to all the new features.A deep dive into new features in macOS Sonoma, big and small.New screen saver experience, desktop widgets, Safari profiles, and more.A new 24-inch iMac is in an "advanced state of development" and could launch as soon as late 2023. A larger model may also be in the works.The Apple Vision Pro AR/VR headset is set to launch in early 2024. It features dual 4K displays, gesture tracking, an M2 chip, and a $3,499 price tag.M3 models in 13.6″ and 15.3″ sizes.Apple's cheapest MacBook Pro should get a speed bump to a new M3 chip.2 days ago by Joe Rossignol2 days ago by Tim Hardwick2 days ago by Tim Hardwick2 days ago by Tim Hardwick2 days ago by Tim Hardwick MacRumors attracts a broad audience of both consumers and professionals interested in the latest technologies and products. We also boast an active community focused on purchasing decisions and technical aspects of the iPhone, iPod, iPad, and Mac platforms.

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