HDL Code To Simulate 1-Bit Comparator
Aim –Simulate 1-Bit Comparator
Basic concepts to understand simulate 1-bit comparator
What is Behavioral Modeling?
- Level of abstraction, where without considering hardware implementation, the desired algorithm is created then such type of modeling is behavioral modeling.
- Similar to C++ coding.
- It shows the behavior of output with respect to the input.
- It is the highest level of abstraction.
module Declaration in Verilog Code
module( ) . . endmodule
- module name should be a valid identifier.
- module terminal list is set of input and output terminal of module.
- module consists of a set of statements which is required to realize module.
always ends with endmodule keyword.
Usage of always Statement
always@ (sensitivity list) begin //all sequential statements end
- Helps to show activity flow.
- Event is occurred due to sensitivity list, then statements inside the always statement execute continuously.Execution of all blocks concurrently.
Why begin, end ?
- If there are multiple statements, then it is necessary to write begin, end statement.
- If there is a single statement, then no need to write begin, end statement.
initial Statement in Verilog Test Bench
initial begin //all sequential statements end
- Helps to show separate activity flow. It is different from always.
- Both initial and always should not be nested.
- Statements inside the initial will execute only once.
- It is used in the simulation.
- It does not execute again.
- For multiple blocks, it executes concurrently.
Difference between Assignment Operator(=) and Equality Operator(==) ?
Assignment Operator(=) Assigns an operand on the left-hand side to the value on the right-hand side.
Equality operator(==) Used to check both operands are equal or not.
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1-Bit Comparator Theory
- Input – a ( 1bit binary 1 or 0), b( 1bit binary 1 or 0) .
- Output- l, e, g.
- l=1 when a=0, b=1.
e=1 for two conditions, a=0 b=1, a=1 and b=1.
g=1 when a=1, b=0.
3 Levels Of Abstraction
- Data Flow Modeling
- Behavioral Modeling
- Structural Modeling
Remember
- Each module can be written in any type of modeling.
- In all styles of modeling, output remains same.
- Verilog Test Bench is also same for all types of modeling.
Data Flow Modeling
- Algorithm ( module) is defined based upon how data is moved from input to output.
- The Designer knows how data flows between hardware registers and how it is processed.
Structural Modelling
- This type of modeling requires knowledge of switch level implementation.
- The module can be implemented in terms of switches, nodes, and interconnection between them.
Verilog Code For Data Flow Modeling
Verilog Code module comp1( input a,b, output l,e,g); assign l= (~a) & b; assign e= ~(a ^ b); assign g= a & (~b); endmodule
- In data flow modeling, dont keep output in register.
- assign l=(~a)&b;// a=0,b=1 then l=1.
- assign e=~(a^b);// two conditions a=0, b=0 and a=1 b=1.
- assign g= a&(~b);// a=1 b=0 then g=1.
Verilog Code For Behavioral Modeling
module COMP_BE( input a,b, output l,e,g ); reg l,e,g; always @(a or b) begin l=1; e=0; g=0; if(a>b) begin l=0; e=0; g=1; end else if (a
- In behavioral modeling, the output should be stored in the register.
- In behavioral modeling, hardware implementations are not considered for the algorithm.
- Codes are similar to c programming codes.
- In this program, we are using if else if conditional statements because of multiple conditions.
Verilog Code For Structural Modeling
module b_comp1 (a, b, l, e,g); input a, b; output l, e, g; wire s1, s2; not X1(s1, a); not X2 (s2, b); and X3 (l,s1, b); and X4 (g,s2, a); xnor X5 (e, a, b); endmodule
- In structural modeling, no need to write reg for output.
wire s1,s2;// temperary memory storage to get ~a and ~b not X1(s1,a); // not of a (~a) is moved to the s1 not X2(s2,b); // not of b (~b) is oved to the s2 and X3 (l,s1,b);// and of s1 and b =(~a)&b is moved to l and X4 (g,s2,a); // and of s2 and a =(~b)&a is oved to g xnor X5( e, a,b); // xnor of a and b is moved to e, e=~(a^b)
Verilog Test Bench
module b_comp1_tb; reg a; reg b; wire l; wire e; wire g; b_comp1 uut (.a(a), .b(b), .l(l), .e(e), .g(g)); initial begin a = 0;b = 0;#100; a = 0;b = 1;#100; a = 1;b = 0;#100; a = 1;b = 1;#100; end endmodule
Output
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