HDL Code To Simulate Full Adder
Aim –Simulate Full Adder
Basic concepts to understand simulate full adder
Basics of Verilog Code
Why need of using high level of abstraction?
- Higher the level of abstraction, more flexible and technology independent design, easily programmed and applied to all machines.
- Lower the level of abstraction like switch level, design becomes inflexible and technology dependent.
case statement declaration syntax
case(control-expression) test-value1: begin statement1; statement2; end test-value2 : begin statement3; statement4; end default: begin statementn; statementp; end
case(temp) //Bracketismust 2’b00:y=a+b; 2’b00:y=a-b; 2’b00:y=a&b; default:y=y; endcase
if statement declaration syntax
if(BooleanExpression) begin statement1; statement2; statement3; end else begin statementa; statementb; statementc; end
else if statement declaration syntax
if(BooleanExpression1) begin statement1;statement2; end elseif(BooleanExpression2) begin statement3;statement4; end . . else begin statementx;statementy; end
if else statement declaration syntax
modulemux1(A,B,Sel,Gbar,Y); inputA,B,Sel,Gbar; outputY; regY; always@(Sel,A,B,Gbar) begin if(Gbar==1) Y=1’bZ; else begin If(Sel) Y=B; else Y=A; end end endmodule
What is instantiation?
- module is like a template, it creates a unique object when it is invoked.
- Each object will have its own name, variable name, i/o interface.
Difference between wire and register
- wire elements are a stateless way of connecting two pieces in a Verilog-based design.
- busses of arbitrary width
- wire elements can only be used to model combinational logic.
- reg is similar to wires but can be used to store information (‘state’) like registers.
- reg can, therefore, be used to create both combinational and sequential logic.
What is simulation?
- Testing of the designed block by applying the stimulus (test bench) and checking results. This process is called stimulation.
Full Adder Theory
DOWNLOAD VERILOG PROGRAMS(SECURE DOWNLOAD)
Verilog Code For Data Flow Modeling
Verilog Code module fa2( input a,b,c, output s,cout ); assign s=(a^b^c); assign cout=(a & b)| (b & c)| (c & a); endmodule
- In data flow modelling, module is based on how data flows between hardware register and how it is processed.
- assign s=(a^b^c); // From the truth table.
- assign cout=(a&b) | (b&c) | (c&a) ;
Verilog Code For Behavioral Modeling
Verilog Code
module fab1(
input cin,x,y,
output s,co);
reg s,co;
always@(cin or x or y)
begin
case ({cin,x,y})
3'b000:{co,s}='b00;
3'b001:{co,s}='b01;
3'b010:{co,s}='b01;
3'b011:{co,s}='b10;
3'b100:{co,s}='b01;
3'b101:{co,s}='b10;
3'b110:{co,s}='b10;
3'b111:{co,s}='b11;
endcase
end
endmodule
- In behavioral modelling, it is important to store output in the register.
- we are using case conditional statements because of multiple conditions.
case ( { a,b,c})
3’b000: { s, cout}=’b00; // 3’b000, 3-3bit, b-binary// if a=0,b=0,c=0 then s=0, cout=0// 2’b00 is similar to ‘b00
3’b001: { s, cout}=’b10;
3’b010: { s, cout}=’b10;
3’b011: { s, cout}=’b01;
3’b100: { s, cout}=’b10;
3’b101: { s, cout}=’b01;
3’b110: { s, cout}=’b01;
3’b111: { s, cout}=’b11;
Verilog Code For Structural Modeling
module fas1( input x,y,z, output cout,sum); wire P1,P2,P3; ha HA1 (P1,P2,x,y); ha HA2 (sum,P3,P1,z); or OR1 (cout,P2,P3); endmodule
- FA- top level module.
- It has 2HA and OR gate
wire P1,P2,P3
//From Logic diagram
ha HA1(a,b,P1,P2); P1=s1, P2=c1
ha HA2(P1,c,sum,P3);
OR OR1( P2,P3,cout)
Verilog Test Bench
module ttfab1; reg cin; reg x; reg y; wire s; wire co; fab1 uut ( .cin(cin), .x(x), .y(y), .s(s), .co(co)); initial begin cin = 0;x = 0;y = 0; #100; cin = 0;x = 0;y = 1; #100; cin = 0;x = 1;y = 0; #100; cin = 0;x = 1;y = 1; #100; cin = 1;x = 0;y = 0; #100; cin = 1;x = 0;y = 1; #100; cin = 1;x = 1;y = 0; #100; cin = 1;x = 1;y = 1; #100; end endmodule
Output
DOWNLOAD VERILOG PROGRAMS(SECURE DOWNLOAD)
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