Intel recently announced the launch of its Lakefield 'system on chip' (SoC) processors: peculiar-looking layered CPUs that allow for more power in a much smaller package. It's difficult to picture exactly how the Foveros 3D packaging technology that’s used to form these CPUs works, so Intel has put a video together showing how the layers stack atop one another… with lego.

The video shows the bottom layer containing front-end I/O modules such as those for storage (NVMe) and PCIe Gen3. The second layer features the main back-end computing modules, including CPU cores, the memory controller, and graphics module. Finally, the top two layers contain eight DRAM modules (with four modules in each layer), completing the four-layer Lakefield stack.

Processors built on the Lakefield architecture should be a good testing ground for the big.LITTLE technology that we might see championed in future Intel Alder Lake-S CPUs. Keeping an eye on how well the big.LITTLE die-stacked Lakefield CPUs do might tell us how likely it is that the next-next generation of Intel Core desktop CPUs will use this technology.

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