SWITCHING LOSSES Calculation Model AND METHOD FOR SELECTING FET TRANSISTOR TECHNOLOGIES APPLIED TO STATIC CONVERTERS 

Author: Edemar de Oliveira Prado 

Advisor: José Renes Pinheiro 

This dissertation presents an analytical model to assist in the calculation of switching losses and a methodology for selecting MOSFETs that with breakdown voltages greater than 100 V. The model was developed based on physical and electrical concepts of the FET structure, considering non-linearities of Miller capacitance as a function of voltage variation, mainly present in MOSFETs manufactured to operate in voltages above 100 V. Simulation and experimental results that validate the model were obtained, considering the frequency range of 1 - 300 kHz, at which the limit of gate driver operation has been reached. The proposed model was compared to other loss calculation models frequently used in the literature, where it was observed that other models show an increase in the relative error for frequencies above 50 kHz. Heat transfer systems are analyzed and discussed. The proposed loss Calculation Model is used in the development of a comparative analysis between the technologies of conventional Silicon MOSFET, superjunction, SiC and GaN. The impact of stray capacitances, junction temperature, intrinsic resistances, switching frequency and power levels in each technology are analyzed. Application trend areas are defined for each technology based on yields as a efficiency of frequency and power.