Digital Design Interview Questions
1. Design a Transmission Gate based XOR. Now, how do you convert it to XNOR? (Without inverting the output)
2. Design a divide-by-3 sequential circuit with 50% duty circle. (Hint: Double the Clock)
3. Design any FSM in VHDL or Verilog.
4. Give two ways of converting a two input NAND gate to an inverter
5. Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the delay of the combinational circuit is greater than your clock signal? (You can't resize the combinational circuit transistors)
6. Draw a Transmission Gate-based D-Latch.
7. Give a circuit to divide frequency of clock cycle by two
8. How do you detect a sequence of "1101" arriving serially from a signal line?
9. How do you detect if two 8-bit signals are same?
10. What are the different Adder circuits you studied?
11. Given a circuit, draw its exact timing response. (I was given a Pseudo Random Signal Generator; you can expect any sequential ckt)
12. Give the truth table for a Half Adder. Give a gate level implementation of the same.
13. What are set up time & hold time constraints? What do they signify? Which one is critical for estimating maximum clock frequency of a circuit?