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Efinix Releases Three RISC-V Software-Defined SoC’s Optimized for Trion FPGA’s

Efinix has announced three RISC-V Software-defined SoC’s based on Charles Papon’s VexRiscv core and optimized for the company’s Trion T8 to T120 FPGA’s. VexRiscv is a 32-bit...



This post first appeared on CNXSoft – Embedded Systems News, please read the originial post: here

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Efinix Releases Three RISC-V Software-Defined SoC’s Optimized for Trion FPGA’s

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