Job Requirements:
1.Understanding Verilog HDL
2.Understanding Deep Submicron effects such as 40nm and below
3.Understanding OCV, DFM, DFY
4.Excellent Block level and Full-chip Physical Design skills
5.Self-motivated, leadership skills and experience working with global teams
6.Minimum 5+ years of ASIC Physical design experience
7.Hands on experience and expertise in Cadence, Synopsys, Magma or Mentor Physical Implementation Tools
8.Should have participated in a minimum of 5 fullchip tapeouts.
Educational Qualification :B.E\B.Tech , M.E\M.Tech
Experience : 5+ years
Location : Hyderabad
Job Description:
The position is for a SDE in the Physical Design Group at AMD Hyderabad responsible to build the next generation APUs (Accelerated Processing Unit). The APU comprises the CPU, GPU and other functions on an integrated monolithic die. This position requires interface with large front-end design teams in US, Canada, Shanghai and India, mentoring new hires and owning an entire chip or portion of the chip from RTL/gates to tapeout.
Click here to apply-online
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