2012-02-04 10:14
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2012-02-04 10:11
Thanks to visit this blog... if u need any of the below seminar topics plz mail me [email protected] Smart-Grid Simulator retargeting VCSVMM technologyALGORITHMIC GRAPH THEORYAN EF… Read More
2012-02-04 10:08
PG text booksif u need soft copy of the textbooks mentioned below can mail me [email protected]_-_Digital_Integrated_Circuits_-_A_Design_PerspectiveKumar, Digital Signal Proc… Read More
2012-02-04 10:05
1. The ________ circuit overcomes the problem of switching caused by jitter on the inputs. A. astable multivibratorB. monostab… Read More
2012-02-04 10:04
26. What is the major advantage of the J-K flip-flop over the S-R flip-flop? A. The J-K flip-flop is much faster.B. The J-K fl… Read More
2012-02-04 10:04
16. A settable flip-flop's normal starting state when power is first applied to a circuit is always the ________ state. A. resetB… Read More
2012-02-04 10:04
11. What would be the output voltage of a 7814 voltage regulator? A. –14 V dcB. +14 V dcC. –8 V dc… Read More
2012-02-04 10:04
A 0.01-F capacitor is recommended by TTL manufacturers for ________ the power supply. A. decouplingB. filteringC. r… Read More
2012-02-04 10:04
21. What is the difference between setup time and hold time? A. Setup time occurs after the active clock edge, hold time occurs before the act… Read More
2012-02-04 09:39
Two capacitors are connected in parallel through a switch. C1= 1uF, C2= 0.25uF. Initially the switch is open, C1 is charged to 10V. What happens if we close the switch? No losses in wires… Read More
2012-02-04 09:35
Verilog code for an FSM with a single process. module fsm (clk, reset, x1, outp); input clk, reset, x1; output outp; reg outp; reg [1:0] state; parameter s1… Read More
2012-02-04 09:34
Verilog code for single-port RAM in read-first mode. module raminfr (clk, en, we, addr, di, do); input clk; input we; input en; input [4:0] addr; input [3:0]… Read More
2012-02-04 09:34
Verilog code for single-port RAM in read-first mode. module raminfr (clk, en, we, addr, di, do); input clk; input we; input en; input [4:0] addr; input [3:0]… Read More
2012-02-04 09:30
Verilog code for an unsigned 8-bit greater or equal comparator. module compar(a, b, cmp); input [7:0] a; input [7:0] b; output cmp; assign cmp = (a >= b) ? 1’b1… Read More
2012-02-04 09:29
Following is the Verilog code for an unsigned 8-bit adder with carry in. module adder(a, b, ci, sum); input [7:0] a; input [7:0] b; input ci; output [7:0] sum; assign su… Read More
2012-02-04 09:28
Verilog code for a 4-to-1 1-bit MUX using an If statement. module mux (a, b, c, d, s, o); input a,b,c,d; input [1:0] s; output o; reg o; always @(a or b or c… Read More
2012-02-04 09:27
Verilog code for an 8-bit shift-left register with a positive-edge clock, serial in and serial out. module shift (clk, si, so); input clk,si; output so; reg [7:0] tm… Read More
2012-02-04 09:25
Verilog code for a 4-bit unsigned up accumulator with an asynchronous clear. module accum (clk, clr, d, q); input clk, clr; input [3:0] d; outpu… Read More
2012-02-04 09:23
Verilog code for a 4-bit unsigned up counter with asynchronous clear. module counter (clk, clr, q); input clk, clr; output [3:0] q; reg [3:0]… Read More
2012-02-04 09:20
Verilog code for a tristate element using a concurrent assignment. module three_st (t, i, o); input t, i; output o; assign o = (~t) ? i: 1’bZ; endmodule Read More
2012-02-04 09:19
Verilog code for a latch with a positive gate. module latch (g, d, q); input g, d; output q; reg q; always @(g or d) begin if (g)… Read More
2012-02-04 09:17
Verilog code for a 4-bit register with a positive-edge clock, asynchronous set and clock enable. module flop (clk, d, ce, pre, q); input clk, ce, pre; input [3:0] d; o… Read More
2012-02-04 09:16
Verilog code for flip-flop with a positive-edge clock. module flop (clk, d, q); input clk, d; output q; reg q; always @(posedge clk) begin q <= d; end endmodu… Read More
2012-02-04 09:08
module pri_encoder_using_assign ( 8 binary_out , // 4 bit binary output 9 encoder_in , // 16-bit input 10 enable // Enable for the encoder 11 ); 12 13 output [3:0] binary_out ;… Read More
2012-02-04 09:07
module pri_encoder_using_if ( 8 binary_out , // 4 bit binary output 9 encoder_in , // 16-bit input 10 enable // Enable for the encoder 11 ); 12 output [3:0] binary_out ; 13 input… Read More
2012-02-04 09:06
module encoder_using_case( 8 binary_out , // 4 bit binary Output 9 encoder_in , // 16-bit Input 10 enable // Enable for the encoder 11 ); 12 output [3:0] binary_out ; 13 input e… Read More
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