HDL code to Simulate 2:4 Decoder

Aim – Simulate of 2:4 Decoder using HDL code.

Basics of 2:4 Decoder to learn simulate 2:4 decoder

1. 2:4 Decoder has 2 inputs and 4 outputs. In this program, a,b are two inputs and y0,y1,y2,y3 are four outputs.
2. en– enable should be active high, in order to get output. If en=0 ( active low), then irrespective of inputs, the output will be zero.

Truth Table

HDL Program To simulate 2:4 Decoder

Verilog Code

module dec2_4 (a,b,en,y0,y1,y2,y3)
input a, b, en;
output y0,y1,y2,y3;
assign y0= (~a) & (~b) & en;
assign y1= (~a) & b & en;
assign y2= a & (~ b) & en;
assign y3= a & b & en;
endmodule

Verilog Test Bench

module dec_tb;
reg a,b,en;
wire y0,y1,y2,y3;
dec2_4 uut (
.a(a), .b(b), .en(en),
.y0(y0), .y1(y1), .y2(y2), .y3(y3));
initial begin
// Initialize Inputs
a = 0;b = 0;en = 1;#100;
a = 0;b = 1;en = 1;#100;
a = 1;b = 0;en = 1;#100;
a = 1;b = 1;en = 1;#100;
a = 0;b = 0;en = 0;#100;
#100;
end
endmodule

Output

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Simulation of 2:4 Decoder using Verilog Code

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