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Intel wants to compile chip packages more flexibly

with the combination of emib and Foveros
Intel will combine its emib and Foveros techniques to be able to compile chip packages more flexibly. In addition, the company will apply larger through silicon vias for vertical stacking.

At the SemiconWest conference in San Francisco, Intel announced new technologies for the flexible assembly of chip packages. According to the manufacturer, the role of the package is somewhat underexposed, but its importance is increasing. A package can contain various chip orders, I / O parts and other components, and contains the important connection to the motherboard.

As chip manufacturers have more difficulty in further reducing the size of chip structures, they need more from architecture improvements and from combining chip sets and packaging. With regard to the latter, Intel announces the use of co-emib, omni-directional interconnect and mdio technologies.

Co-emib is the combination of emib, or embedded that interconnect bridge , with Foveros. Emib is Intel’s technology to connect chip components on a substrate with embedded silicon ‘bridges’ with high bandwidth instead of with a large silicon interconnect . The technology enables the company to assemble chips as block boxes. Intel already uses emib to connect fpgas to memory and with Kaby Lake-G processors to let the Radeon-gpu communicate with hbm.

Foveros is the name that Intel gives to stacking chips and connecting them to vertical tsv channels, or through silicon vias . The bottom layer is the I / O interposer that communicates through the TSVs with processor and memory dies on top of that. Intel has demonstrated the use of Foveros with a Lakefield chip, combining four fuel-efficient Atom cores with a powerful Sunny Cove core at 10nm with an interposer at 22nm. Just like with emib, one of the advantages of Foveros is being able to combine chip parts that are made using different production processes.

With co-emib, Intel combines emib with two or more Foveros elements to provide “a single chip” performance. According to Intel, the combination can also connect memory and other blocks at high bandwidth.

In line with this there is the odi, or omni-directional interconnect . This new interconnect allows the horizontal connection of chipsets, but can also be used vertically, whereby the bandwidth is higher than with traditional TSVs. The larger TSV channels also have less resistance, deliver more power and offer lower latency, according to Intel. The advantage is that fewer vertical channels are required through the stacked layers so that more space is left for, for example, transistors.

Intel Semicon West 2019Intel Semicon West 2019Intel Semicon West 2019
Images: Ashel Sag

Finally, there is mdio, which probably stands for multi-die i / o and with which Intel builds on its advanced interface bus standard. The new interface more than doubles the pin speed compared to the AIB standard, the bandwidth is increased and there are also improvements in energy efficiency.

It is not yet known when Intel will apply the techniques in practice. The company only announces that they are used for ‘product architectures of future generations’. For its Ryzen 3000 generation, competitor AMD uses the Infinity Fabric link to connect chipsets and the company is also working on stacking dram and sram on processors with TSV connections.

Intel co-emib Semicon 2019



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Intel wants to compile chip packages more flexibly

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