Job ID : 20171215005

Company : Cisco

Job Role : ASIC design and Verification engineer

Eligibility : Graduate

Experience : 5-7 Years

Job Location : Bangalore

Salary : Not Mentioned

Vacancies : Not Mentioned

Website : www.cisco.com

Description :

• Strong problem solving and ASIC debugging skills
• MSEE with 5+ or BSEE with 7+ years of related experience is required
• Proficient in Verilog
• Have extensive experience in ASIC front end design
• Extensive experience in ASIC verification using Verilog/System Verilog/C
• Experience with verification methodology like OVM/VMM/UVM desired
• Experience in formal verification is desirable
• Experience designing ASICs for networking protocols (Ethernet, FC) a plus
• Must be strong at documenting the verification plan and presentations
• Constrained-random verification a strong plus
• Have experience in formal verification
• Perl/Python/Makefiles scripting is strongly preferred

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