These days I am working on System Verilog/VMM (for those lucky one who don't know what these are, System Verilog is a Hardware Verification Language which is used for verifying complex multi-million gates digital designs, and VMM is a verification methodology for the same):- Presentations:- SV - DesignSV - TestbenchSV - AssertionSV - DPISV - Tranings (133 slides) And many more such presentations