HDL code to simulate 8:3 priority encoder

Aim –Simulate 8:3 priority encoder 

Basic concepts to understand simulate 8:3 priority encoder

Priority Encoder Theory

• In priority encoder, there are 8 inputs, 1 enable signal and 3 outputs.
• In this program, we are using [7:0]i==i[7], i[6], i[5], i[4], i[3], i[2], i[1], i[0] as inputs.
• en – enable signal
• [2:0]y == y[0], y[1], y[2] as 3 outputs.
• Enable signal is active high in priority encoder.
• If en=1, then an only output is produced.
• If en=0, irrespective of input signal output is zero.

Program Code Explaination

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1) module declaration in verilog code

syntax: 

module( )
.

.
endmodule

• module name should be valid identifier.
• module terminal list is set of input and output terminal of module.
• module consists of a set of statements which is required to realize module.
  always ends with endmodule keyword.

2) Level of abstraction used– Behavioral Modeling.

3) What is behavioral modeling?

• Level of abstraction, where without considering hardware implementation, the desired algorithm is created then such type of modeling is behavioral modeling.
• Similar to C++ coding.
• It shows the behavior of output with respect to the input.

4) always statement

• Helps to show activity flow.
• Event is occurred due to sensitivity list, then statements inside the always statement execute continuously.Execution of all blocks concurrently.

Structure of always statement

always@ (sensitivity list)
begin
//all sequential statements
end

why begin, end? 

• If there are multiple statements, then it is necessary to keep begin, end.
• If there is a single statement, then no need to write begin, end.

5)initial statement

• Helps to show separate activity flow. It is different from always.
• Both initial and always should not be nested.
• Statements inside the initial will execute only once.
• It is used in the simulation.
• It does not execute again.
• For multiple blocks, it executes concurrently.

Structure of initial statement

initial 
begin
//all sequential statements
end

why begin, end?

• For multiple statements only, initial and begin is required. For single statements no need to use it.

6) Verilog code to simulate 8:3 priority encoder

• As already discussed always, In this program sensitivity lists are en, i. Because output depends on this two only, that’s why they are sensitive.
  always @ (en,i)
  begin// As there are multiple sequential statements are there so, begin, end
  // sequential statements
  end
•  Initially,  we are checking the status of enable signal because if en=0, then the output is zero irrespective of any input signal.en=1, output is formed based on input signal.
• So, our primary first focus is the status of enable signal.
• if enable signal==0
  begin // because many statements are there inside if statement so begin, end.
  // output is produced depends on input
  end
  else output is zero

How is output produced depending upon input inside if statement?

• if i[7] == 1 then y=111 // We are using nested if because we have multiple conditions. No need to use initial begin for this if statement because only one statement y=111.
• else if i[6]== 1 then y=110.
• else y=000 // this is if all above conditions not satisfied if the input is not given even though enable signal is 1.

7) Verilog Test Bench

• Already discussed the usage of initial, begin in simulation.
• As there are multiple lines inside initial, we are using begin, end.
  Initialise input to check output
  i=128; en=1; // i[7:0], so i=128 means1XXXXXXX in priority encoder
  i=64; en=1;//i[7:0], so i=64 means01XXXXXX in priority encoder
  i=32; en=1;//i[7:0], so i=32 means001XXXXX in priority encoder
  i=16; en=1;//i[7:0], so i=16 means0001XXXX in priority encoder
  i=8; en=1;//i[7:0], so i=8 means 00001XXX in priority encoder
  i=4; en=1;//i[7:0], so i=4 means 000001XX in priority encoder
  i=2; en=1;//i[7:0], so i=2 means 0000001X in priority encoder
  i=1; en=1;//i[7:0], so i=1 means 00000001 in priority encoder

HDL Program to simulate 8:3 priority encoder

Verilog code

module prienc(
input [7:0] i,
input en,
output reg [2:0] y
);
always @ (en,i)
begin
if(en==1)
begin
if ( i[7]==1 ) y=3'b111;
else if ( i[6]==1) y=3'b110;
else if ( i[5]==1 ) y=3'b101;
else if ( i[4]==1 ) y=3'b100;
else if ( i[3]==1 ) y=3'b011;
else if ( i[2]==1 ) y=3'b010;
else if ( i[1]==1 ) y=3'b001;
else if ( i[0]==1 ) y=3'b000;
else  y=3'b000;
end
else
y=3'b000;

end
endmodule

Veilog Test Bench

module prienc_tb;
reg [7:0] i;
reg en;
wire [2:0] y;
prienc uut (
.i(i),
.en(en),
.y(y));
initial
begin
i =128;en = 1;#100;
i =64 ;en = 1;#100;
i =32 ;en = 1;#100;
i =16 ;en = 1;#100;
i =8 ;en = 1;#100;
i =4 ;en = 1;#100;
i =2 ;en = 1;#100;
i =1 ;en = 1;#100;

end
endmodule

Output 

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